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In this paper we have proposed a novel buffer amplifier to be used in LCD circuitry. The circuit is implemented on 0.18μm CMOS technology. The new high speed buffer shows the reduction in the value of settling time and also the power dissipation. The settling time of the output buffer for 1000 pF load is 0.94μs. The power consumption for this circuit is 50.89 μWatts. The gain of the new high speed...
This paper presents a 32 kHz input and 960 MHz output low-power charge-pump phase-locked loop (CP-PLL) with a novel dual-path loop-filter for resistor noise reduction technique. The resistor noise reduction technique using dual-path loop-filter involves no “additional” active component; area/power overhead compared to the conventional CP-PLL. Reverse sub-threshold leakage compensated source-switched...
This paper presents a novel single Z-source based seven level multilevel inverter. In this topology single Z-source impedance network is used to boost up the output voltage using shoot through state control. A new PWM technique is implemented by using three reference signals and a triangular carrier signal which are used to generate the PWM signals for inverter switches, and the shoot through state...
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