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Recently, hetero-integrated system (3-D super chip, Fig. 1) involving memory, processor, power ICs, sensor, and photonic circuits has attracted attention owing to its high performance, highspeed communication, multi-functionality, and low power consumption [1-2]. However, heterointegration of devices with different functions has many technical challenges owing to various types of size, thickness,...
The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even...
Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated...
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