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Latch based arrays are commonly used as small embedded memories. There are often a large number of such memories in a design. Due to the large area overhead of memory BISTs, scan is often used to test such memories. In this paper we show that with a minor modification of a marching sequence targeting only the transition delay faults at the latch boundaries, a comprehensive set of faults can be detected...
Given a set of memory array faults, the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults...
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