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An 11.3Gb/s CMOS SONET-compliant transceiver is designed to work in both RZ and NRZ data formats. The TX driver exhibits 17ps rise/fall times, 0.25psrms RJ, and 2pspp DJ. The RX has a multi-stage vertical threshold adjustment circuit. It achieves 5mVpp-diff RX input sensitivity with 0.54UI jitter tolerance. The transceiver core area occupies 1.36mm2 in 65nm CMOS and consumes 214mW.
We propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors. In the new clocking scheme, injection-locked oscillators are used as local clock receivers. Compared to conventional clocking with buffered trees or grids, ILC can achieve better power efficiency, lower jitter, and much simpler skew compensation...
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