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A 16-b, 1MSps successive approximation ADC in 180nm CMOS uses the ??split ADC?? architecture to enable continuous, all-digital, background self-calibration of ADC linearity. Convergence of calibration parameters to noise-limited accuracy is demonstrated with an adaptation time constant less than 300ms. In the capacitive DAC, a novel segmentation and shuffling approach is used to mitigate requirements...
The “split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a successive approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half-sized...
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