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This paper describes an interconnect technique for subthreshold circuits to improve global wire delay and reduce the delay variation due to process-voltage-temperature (PVT) fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from subthreshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. Simulations...
This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network...
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