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In this paper, a novel low-power class-AB CMOS OTA with high slew-rate is presented. The proposed OTA is based on class-AB input stage using a novel adaptive-biasing. The proposed OTA designed using a standard 0.18-um CMOS technology indicates that rising and falling slew-rates of +4.92 V/??S and -5.04 V/??S with worst-case settling time of 2.1 ??S, a voltage gain of 48.97 dB with GBW of 57.27 kHz...
An embedded DAC requires a large number of input transistors (=2N+1 for N-bit interpolation) in its amplifier. Moreover, the transistors require large width and length for accurate matching, leading to an area penalty in the amplifier for high bit interpolation (e.g. N>3). In this paper, an area-efficient and accurate interpolation method that uses variable-current control (VCC) for 10b mobile...
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