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Numerical simulation of micro-bumped flip chips mounted on a TSV interposer is conducted to study the thermal performance of the package. The 3D package, which consists of two chips, each dissipating 4W, is evaluated under various conditions with its thermal resistances θja θjb, θjc and θjma determined according to JEDEC or MIL-STD standard. Instead of building the detailed model, equivalent thermal...
Because of Moore's (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch...
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