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This paper presents a low-power and small-area VCO-based closed-loop ΔΣ ADC with two highlights. First, the ADC has a distributed modular architecture. It consists of repetitive slices, which simplifies both schematic and layout design. It allows the ADC to be easily reconfigured for other resolution specifications. Second, a novel digital DAC mismatch calibration technique is proposed. It has low...
This paper presents a random dynamic element matching (DEM) technique for current-steering digital-to-analog converters (DACs). It randomizes the element selection process, and keeps the number of transitions to minimum. As a result, it does not introduce extra dynamic errors caused by inter-symbol interference (ISI). This technique also alleviates the impact of linear gradient errors due to the fabrication...
This paper presents a simple but high performance architecture for multi-channel analog-to-digital conversion. Based on compressive sensing, only one SAR ADC is needed to convert multi-channel sparse inputs, leading to significant analog power saving and hardware saving. Moreover, it helps avoid problems occurring in conventional multi-channel ADCs such as timing skew, offset mismatch, and gain mismatch...
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