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Advanced junction scaling with device performance gain, leakage reduction and reduced threshold voltage (Vth) variation are critical for CMOS 28nm node and future scaling. In this paper, implant induced defect engineering for higher drive current with reduced SRAM defectivity, advanced junction formation and Vth mismatch (Vtmin) on a state-of-the-art 28nm logic flow are demonstrated and discussed.
In this paper, we have demonstrated that cryogenic implantation applied to source and drain (SD) extension, pocket/halo and SD formation offers advantages for higher core and SRAM driving current and one order lower Ioff bulk (Ioffb) leakage in NMOS with reduced SRAM defectivity. Atomistic Kinetic Monte Carlo (KMC) modeling confirms that the cryo-implantation has enabled a unique control of active...
Strain techniques have been adopted and widely used in the advanced nodes since early 65nm for carrier mobility improvement. For PMOS, eSiGe incorporation in the SD is the process of choice to induce compressive strain in the channel for mobility improvement. To further lower the contact resistance, it is preferred to boost Boron concentration for pSD formed by eSiGe process. Normal implant process...
In this letter, for the first time, the integration benefits of a molecular carborane (CBH-C2B10H12) implant on a state-of-the-art 28-nm logic flow are demonstrated and discussed via advanced modeling. It is shown that, by integrating CBH, pLDD formation can be optimized to provide device benefits via profile/damage engineering.
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