The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Die-stacked DRAM (a.k.a., on-chip DRAM) provides much higher bandwidth and lower latency than off-chip DRAM. It is a promising technology to break the "memory wall". Die-stacked DRAM can be used either as a cache (i.e., DRAM cache) or as a part of memory (PoM). A DRAM cache design would suffer from more page faults than a PoM design as the DRAM cache cannot contribute towards capacity of...
As we continue toward exascale, scientific data volume is continuing to scale and becoming more burdensome to manage. In this paper, we lay out opportunities to enhance state of the art data management techniques. We emphasize well-principled data compression, and using it to achieve progressive refinement. This can both accelerate I/O and afford the user increased flexibility when she interacts with...
Improving read performance is one of the major challenges with speeding up scientific data analytic applications. Utilizing the memory hierarchy is one major line of researches to address the read performance bottleneck. Related methods usually combine solide-state-drives(SSDs) with dynamic random-access memory(DRAM) and/or parallel file system(PFS) to mitigate the speed and space gap between DRAM...
Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described. Thick- and thin-Bottom Oxide (BOX) variants are discussed.
This paper aims at speeding up RSA decryption. EAPRSA (Encrypt Assistant Multi-Power RSA) is proposed to improve RSA decryption performance by transferring some decryption computations to encryption. The experimental result shows that the speed of the decryption has been substantially improved and the variant can be efficiently implemented in parallel.
This paper aims at speeding up Batch RSA decryption. BEARSA (Batch Encrypt Assistant RSA) and BEAMRSA (Batch Encrypt Assistant Multi-Prime RSA) are proposed to improve Batch RSA decryption performance. Two variants of Batch RSA speed up decryption by reducing modules in modular exponentiation and shifting some decryption work to encryption. The experimental results and the theoretical values show...
This paper aims at speeding up RSA decryption and signature. The performance of RSA decryption and signature has direct relationship with the efficiency of modular exponentiation implementation. This paper proposes a variant of RSA cryptosystem (EAMRSA-Encrypt Assistant Multi- Prime RSA) by reducing modules and private exponents in modular exponentiation. The experimental result shows that the speed...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.