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A high performance CMOS HK/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff = 100 nA/μm with VDD = 1 V are 1.25 mA/μm and 0.56 mA/μm for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region. The PMOS -0.25V Vt @1um Lg and NBTI 10 years life time @0.7V overdrive...
The impact on the reliability of capping layers for low Vt nMOS and pMOS high-k transistors with metal gate is investigated and devices without the resist and strip process are compared to different resist removal recipes. It is found that the interface is not affected by the cap layer, but during the resist removal a thin defect layer is created. While with the cap above the host dielectric the impact...
PBTI and NBTI reliability is investigated on La2O3 and Al2O3 capped n and pMOSFETs, respectively. Low Vth devices are achieved using the capping layers without degrading BTI reliability. For the Al2O3 capped pMOSFETs no additional defects related to the capping are observed. The La2O3 capping layer for nMOSFETs induces shallow traps, which however are not critical at operating conditions.
In this work, by employing a sub-monolayer HfSiON cap (via ALD deposition) on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices, we report that 1) the devices (both n-FETs and p-FETs) V, is effectively modulated likely due to the Fermi-level pinning relaxation; 2) the gate leakage is significantly reduced; 3) the dielectrics reliability characteristics (such as TZBD, pFETs NBTI,...
This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: 1) both cases...
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