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Models of spatial variation in images are central to a large number of low-level computer vision problems including segmentation, registration, and 3D structure detection. Often, images are represented using parametric models to characterize (noise-free) image variation, and, additive noise. However, the noise model may be unknown and parametric models may only be valid on individual segments of the...
An 11G VCO in 45-nm CMOS employing high Vth switching core devices for improved phase noise is presented for integrated base station RF transceivers for 3GPP applications. The VCO in combination with on-chip PLL is used for clocking on-chip multi-GHz data converters. It provides an in-depth coverage into device type selection for improved phase noise to meet 3GPP specifications. It also evaluates...
This paper describes our work with the SimpleScalar simulator and the comparison of different cache models on the SimpleScalar architecture. The toolset can model simulations for a variety of platforms ranging from simple unpipelined processors to detailed dynamically scheduled microarchitectures with multiple-level memory hierarchies. However, inefficient caching increases the access time and reduces...
This paper presents a novel scheme for avoiding congestion in the field of wireless sensor networks. Our new scheme provides a priority based approach for wireless sensor cluster network to reduce traffic load using congestion aware routing (CAR). It proposes the new mechanism for the purpose of mitigating congestion which enhances the performance of the network. The proposed mechanism uses congestion...
A 5.9-to-8.0 GHz fractional-N digital PLL with TDC histogram calibration, reference doubler compensation and non-periodic DCO dithering is implemented in 55nm CMOS. With reference doubled from 40 MHz, the rms jitter integrated from 1kHz to 10MHz is 0.19ps or 0.4° for a 5825 MHz clock measured at TX output, and the in-band noise floor is −108 dBc/Hz. The reference and worst-case fractional spurs are...
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