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Defects-induced contact misalignment when combining embedded SiGe with flash lamp annealing (FLA) on high performance 40 nm CMOS process has been analyzed both by experiments and novel dislocation loop dynamics simulation. We have found that slips which are created at the SiGe dummy patterns worsen the contact misalignment for the first time. Design guide lines on shape of SiGe patterns for slip free...
For the first time, we demonstrate standard cell gate density of 3650 KGate/mm2 and SRAM cell of 0.124 mum2 for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45 nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP)...
Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin...
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