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Vector-SIMD architectures have gained increasing attention because of their high performance in signal-processing applications. However, the performance of existing vector-SIMD architectures remains limited because of their inefficiency in the coordinated exploitation of different hardware units. To solve this problem, this article proposes the FT-Matrix architecture, which improves the coordination...
The shuffle operation is one of the bottlenecks invector DSPs. The partitioning problem of the shuffle matrix will have a great effect on the design of the shuffle unit, when dealing with the small grain data shuffle using a smaller-sized crossbar. The traditional matrix block partitioning solution will bring much chip area, power consumption and critical path delay. This paper presents a new matrix...
Heterogeneous multicore processor can integrate merits of different architecture, so it can achieve peak performance as high as processors with special architecture, while keeping as flexible as traditional general purpose processors at the same time. It is a challenge to design a memory sub-system for FT64-3, which is a heterogeneous multicore processor with 18 float function units. In this paper,...
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