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This paper presents a Vector DMA Cache (VDC)scheme between the DMA bus and the Vector Memory (VM) in vector DSPs. The VDC can effectively reduce the VM access counts from the DMA requests and decrease the VM access conflicts. The VDC is specially designed for the DMA and not for the CPU, so it has some unique techniques which differ from the traditional CPU cache scheme. The main techniques of the...
Heterogeneous multicore processor can integrate merits of different architecture, so it can achieve peak performance as high as processors with special architecture, while keeping as flexible as traditional general purpose processors at the same time. It is a challenge to design a memory sub-system for FT64-3, which is a heterogeneous multicore processor with 18 float function units. In this paper,...
Flight delay early warning can reduce the negative impact of the delay. Determining the delay grade of each interval is essentially a multi-class classification problem. This paper presents a flight delay early warning model based on a fuzzy support vector machine with weighted margin (WMSVM) , which adjust the penalties to samples and the margins between samples and the hyperplane according to the...
Ranking support vector machine (RSVM) learning is equivalent to solving a convex quadratic programming problem. Currently there exists some difficulties for exact online ranking learning. This paper presents an exact and effective method that can solve the online ranking learning problem and shows the feasibility and finite convergence of the algorithm from the perspective of theoretical analysis...
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