The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Recent days, Tunnel FETs are the potential replacement of conventional MOSFET. And, germanium (Ge) is considered to be a good alternative of Si as channel material of TFET to boost the on current. However, the variation in lattice temperature is a crucial issue in device performance as it modulates the band gap narrowing and hence tunneling characteristics of TFETs. In this study, we report on the...
In this work, we present an analytical model for studying the sub-threshold charge leakage in nanocrystal embedded gate dielectric DGMOSFET Non Volatile Memories. From a parabolic approximation based method, we evaluate the surface potential and the threshold voltage in such a device. Thereafter using the WKB approximation, the charge leakage from the nanocrystal layer to the Si substrate under sub-threshold...
In this paper, we present a simple and accurate method to extract the parasitic as well as the intrinsic components of a Bulk FinFET device. Based on the Y- parameter data obtained from the 3-dimensional device simulator Sentaurus TCAD, the parasitic components are de-embedded and an accurate modeling based on the equivalent small signal circuit is presented to extract the intrinsic parameters. The...
An analytical sub-threshold surface potential model for double gate MOSFET (DG-MOSFET) is presented incorporating the edge effects at the source and drain ends. As the gate length of DG MOSFETs is scaled down, the barrier lowering becomes very important. A fitting parameter α is introduced to compensate this effect. The results obtained with this modeled equation are well matched with the results...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.