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In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the...
In this paper, novel reconfigurable architectures are introduced to utilize high-density resistive memory (RRAM) to build FPGA components. Different from the existing CMOS-nano hybrid circuits that use crossbars, the proposed rFPGA structures consist of mainly 1T1R structures (1 CMOS transistor is integrated with a two-terminal resistive nanojunction) that can be fabricated using a CMOS-compatible...
New designs of Redundant Binary full Adders are proposed for redundant binary system, and implemented using 0.18 mum CMOS technology. The proposed full adder designs require low number of transistors and show lower power dissipation and reduced time delay compared to currently available designs. These new designs can be widely used for computer arithmetic units in redundant binary systems. As case...
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