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Proposed is a two-stage amplifier exploiting recycling current-buffer Miller compensation (CBMC). By reusing the most current-consuming devices in the 1st stage as current buffer, such an amplifier not only can preserve the merits of typical CBMC implementation in creating the beneficial left-half-plane (LHP) zero, but also can avoid the drawbacks of typical CBMC scheme from degrading the power efficiency,...
This paper presents novel sub-harmonic mixer topologies for W-band automotive radar applications in 65nm CMOS technology. Working principle and performance of three kinds of topologies are analyzed and discussed with physical layout and EM simulation. The simulated performance shows a double side band noise figure of 20.8 dB and a voltage conversion gain of −8.7 dB at an RF frequency of 79.0001 GHz...
A novel stacked FET digital-to-RF converter is implemented in 45-nm SOI CMOS, which shares DC current through an I/Q digital-to-analog converter (DAC), I/Q mixer, and stacked-FET PA to provide high output power. The proposed architecture transmits at 1.25 Gbps for QPSK at 45GHz. This transmitter exhibits a 21.3-dBm saturated output power, while achieving a peak PAE of 16%. The circuit occupies 0.3mm...
In this paper, a V-band dual-conversion down-converter with a silicon-based Schottky diode using low-doped N-well for DC and RF characteristics optimization is demonstrated in standard 0.18 μm CMOS technology. A triple-balanced subharmonic Schottky diode microwave mixer and a double-balanced resistive analog mixer are employed as the first conversion mixer and the second conversion mixer, respectively...
This paper presents an innovative architecture for the active quasi-circulator to break the structural limitation on the leakage suppression. A practical prototype is implemented at K -band and fabricated by using standard 0.18- μm 1P6M CMOS technology. The comparisons between simulations and on-wafer measurements are reported in detail to confirm the feasibility and capability of the proposed active...
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