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Identifying speed-limiting paths is crucial for design stepping in which problematic paths are fixed or optimized so as to reach higher clock rates. Recently, using at-speed scan test patterns to identify speed-limiting paths has been reported to be a robust and effective solution. In this paper, we propose a systematic approach to find suspect path expressions (SPE) that explain the observed failing...
Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the portable applications. Design is tested for various substrate bias voltages in sub-threshold region to opt for better design. Design comparison between previously reported design and modified design...
In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using master-slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and...
The radio frequency identification system (RFID) is becoming one of the most popular system in wireless technologies. The UHF RFID tag emulator is a part of RFID testing tools. The UHF RFID tag emulator would be imitating the behavior of RFID Tag. The UHF RFID tag emulator (860 MHz to 960 MHz) is aimed for testing the RFID systems and also acts as a general-purpose data transport device for other...
Low power consumption is a key requirement in mobile and other embedded applications. Accurate power estimation during design phase is a key enabler for designing a power optimized SoC. Abstracting accurate power models for complex IPs such as embedded memories is a challenging task. At the same time, the complex modules have a large share in total power consumption of an IC. In this paper we analyze...
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