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The multi-stack process on wafer-on-wafer (WOW) has been developed. In order to realize the multi-stacked wafer with ultra thinned wafer of less than 10 μm with adhesive polymer, several processes have been optimized. The wafer thickness after back-grinding was controlled within the total thickness variation (TTV) of 1.2 μm on wafer-level of 8 inch. For the side wall of though silicon vias (TSV),...
With evaluation of various dense silicon-oxy-nitride (SiON) films, a critical density and thickness against to Cu diffusion into Si substrate has been evaluated. Density of SiON films varied with deposition temperature using Plasma-Enhanced Chemical-Vapor-Deposition (PECVD) was ranged from 56% to 69% for bulk film. Cu diffusion increased with decreasing the film density, resulting in 3.5 × 1010 cm...
Through-silicon via (TSV) module-process based on wafer-on-wafer (WOW) stacking has been developed. Stacking wafers were thinned down to 20 μm, and TSVs with a diameter of 30 μm were fabricated to connect inter-wafers without electrical failure in chain TSV interconnects. The TSVs were constructed with the damascene technique. Multi-wafer stacking was realized by planarizing TSV-heads with a diamond...
High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7-μm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff,...
In the through silicon via (TSV) structure for 3-dimentional integration (3DI), large thermal-mechanical stress acts in the BEOL layer caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. The resulting high-stress region is thought to be the critical point for the initiation of the cracking or the de-lamination that affects the mechanical reliability. In this study,...
The fabrication of WOW (wafer-on-a-wafer) with MEMS technology has been developed. A wafer was thinned and stacked on a base wafer. After the TSVs were patterned on the thinned wafer, they were filled by Cu for interconnection. The wafers were bonded with benzocylcobutene (BCB, CYCLOTENETM) as an adhesive material. The BCB layer was also acted as a dielectric layer between top and bottom silicon wafers...
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