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A Flexible and Transparent charge trap Memory (FTM) based on a single-layer graphene (SLG) channel with a ITO gate electrode was fabricated on a flexible and transparent poly-ethylene naphtalate (PEN) substrate. Triple high-k dielectric stacks Al2O3- AlOx-Al2O3 (AAA) were used as a data storage layer. The FTM shows memory characteristics with a memory window larger than 7V while maintaining ~80% of...
A The non-volatile gEOTMs are fabricated using a single-layer graphene (SLG) channel with an Al2O3 gate oxide layer, in which an ion-bombarded AlOx layer is intentionally formed by oxygen ion bombardment (OIB) to create the charge trap sites. The whole processes are carried out at temperature below 120°C to exploit gEOTM's compatibility to the flexible substrates. The devices shows a large memory...
A novel 3-D NAND flash memory device, VSAT (Vertical-Stacked-Array-Transistor), has successfully been achieved. The VSAT was realized through a cost-effective and straightforward process called PIPE (planarized-Integration-on-the-same-plane). The VSAT combined with PIPE forms a unique 3-D vertical integration method that may be exploited for ultra-high-density Flash memory chip and solid-state-drive...
A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/ mum for n-channel and 1.30 mA/ mum for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to...
Modifying the multi-bridge-channel MOSFET (MBCFET) process, we have successfully fabricated single-bridge-channel MOSFET (SBCFET). Due to reduced epitaxial growth steps and simple ion implantation process, the SBCFET has manufacture-worthy simple fabrication process like conventional planar transistor. The current drivability of SBCFET shows 2.0 mA/mum @ 100 pA/mum off-current in 1.0 V operation
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