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A 4 Gb flash memory, fabricated in 90 nm CMOS technology, results in a 126 mm/sup 2/ chip size and a 0.0162 /spl mu/m/sup 2//b cell size. Address and temperature compensation methods control the resistance of the inversion-layer local bit-line. A programming throughput of 10 MB/s is achieved by using a self-boosted charge injection scheme.
A method for copying memory cells to reduce the size of the register file for a multi-threaded processor is proposed. The number of transistors in the memory cell is reduced to 70% and the total bit and word lines is reduced to 63%. The register file is implemented in a 100nm CMOS process. The size of the register file is reduced to 62% of a conventional register file. The power consumption is reduced...
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