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Spin transfer torque magnetic random access memory (STT-MRAM) is recommended as one of the promising candidates for nonvolatile memory technologies. Compared with traditional memory technologies, STT-MRAM demonstrates low power consumption, fast access speed and infinite endurance, while the storage capacity reported so far has not been that large in contrast with SRAM or DRAM. Considering this, multi-level...
Conventional spin-transfer torque random access memory (STT-RAM) is a promising technology due to its non-volatility and dense cell structure. However, the long switching time of magnetic tunneling junction (MTJ) limits the write speed of the STT-RAM. In order to improve the write performance, a Spin-Hall Effect (SHE) assisted STT-RAM structure (SHE-RAM) has recently been proposed [1]. SHE effect...
The future of computational electromagnetics is CHANGING DRASTICALLY with the new generation of computer chips which are multi-core instead of single core. Previously, advancements in chip technology meant an increase in clock speed, which was typically a benefit that computational code users could enjoy. This is no longer the case. In the new roadmaps for chip manufacturers, speed has been sacrificed...
As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies such as FeRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and...
This document presents a new automatic goal oriented optimizer using a parallel higher order based integral equation solver (HOBBIES). This automatic goal oriented optimizer has some important features such as user-friendly multiplatform graphical user interface and the support of remote execution on high performance computing cluster. In order to illustrate the functionality and capabilities of this...
This paper proposes a programmable Built-In Self-Test (BIST) approach for DRAM test and diagnosis. The proposed architecture suits well for embedded core testing as well as for stacked and stand-alone DRAMs and it provides programmability features for executing both March and NPSF-oriented test algorithms. The proposed BIST structure is designed to be easily customized with memory topology parameters...
The objective of this paper is to illustrate how these problems can be best handled on scalable affordable personal computer clusters. The authors propose to achieve this goal through the use of out-of-core matrix solvers. Since, the authors do not require RAM but hard disk to deal with the storage, now the problem can be handled at an affordable personal level. Examples are presented on how this...
FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed...
We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 μm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated...
A leading edge 32 nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric...
CMOS technology has followed Moore's law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role...
Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell,...
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