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We report on gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7Å EOT, ∼2x higher fmax performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence. Additional key features: 1) scavenging technique yielding UT-EOT down to ∼5Å is demonstrated in gate-last,...
In this paper, Si-MOS capacitors with HfTiO/SiON stack gate dielectric were fabricated by using Si-surface thermal passivation in NO and N2O ambients respectively and reactive co-sputtering technology. Results show that the sample pretreated in NO ambient has excellent interface properties, low gate leakage current density and high reliability. This is attributed to the formation of a SiON interlayer...
The paper reports the impact of TiN metal gate composition (Ti-rich vs. N-rich) and preparation methodology (atomic layer deposition-ALD vs. physical vapor deposition -PVD) on its thermal stability with HfO2 high-K dielectric, via both physical characterization (X-ray Photoelectron Spectroscopy-XPS, High Resolution TEM combined with Electron Energy Loss Spectroscopy-EELS), and electrical characterization...
We report on the low-frequency phase-noise measurements of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors employing HfAlO as the gate dielectric. Some devices tested exhibited noise spectra deviating from the well-known 1/fγ spectrum. These devices showed broad peaks in the noise spectral density versus frequency plots, which shifted toward higher frequencies at elevated...
For NiSi FUSI gate transistors, switching behaviors have been observed after breakdown (BD) under certain favorable conditions. The conductive BD path can be ??switched-off?? if a reverse bias, as opposed to the stressing voltage, is applied, a condition required for observing SET and RESET conduction in switching material systems. Using the percolation model of BD of gate dielectric systems, we explain...
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