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This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of power and voltage level at the sum and carry nodes. The proposed circuit performance is compared with a...
As day by day continuing research in the field of nanotechnology, the CMOS manufacturing process scaled down in nano-dimensions at the cost of severe process variations and high leakage current which resulting large power dissipation. Therefore the leakage current and power dissipation becomes increasingly more focused in VLSI circuit design. Carbon NanoTube Field Effect Transistor (CNFETs) is suited...
With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra low power circuit designs. Over the years, adiabatic circuit designs have been studied and found to be effective in achieving low power in VLSI circuits. This paper briefs some of the adiabatic logic families such as ECRL, 2N-2N2P and PFAL. And...
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power consumption under control. As a consequence, the transistor...
Dynamic domino logic circuits are used for high system performance. The dynamic circuits offer superior speed and power dissipation over static CMOS circuits. But these circuits suffer from limitations such as charge leakage, noise and charge sharing. This article provides analysis of the different keeper topologies on pseudo domino logic circuits with reference to power dissipation. The circuit simulations...
The progress towards making efficient chips, in terms of area, speed and power continues to remain a major concern of every silicon industry. The various effects that become prominent at nanometer level hinders this progress. This is a paper that looks into: scaling, its effects (short-channel effects, as it is called) and compares scaled single gate and scaled multiple gate FETs on important properties...
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