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In this paper, firstly, we have calculated the delay through an ideal RLC transmission line model, without the driver and the load impedance. This yield's to the transform voltage and current equations governing the system response by incorporating appropriate boundary conditions for interconnect delay analysis. Two port parameters in terms of ABCD matrix are obtained. Further we considered a practical...
In deep sub-micrometer (DSM) regime the on-chip interconnect delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. By interpreting the impulse response of a linear circuit as a probability distribution function (PDF), Elmore first estimated the interconnect delay. Several other approaches like...
Slew rate determines the ability of a device to handle the varying signals. Determination of the slew rate to a good proximity is thus essential for efficient design of high speed CMOS integrated circuits. This in turn reduces the output switching surges in the device. Interconnect slew has become a crucial bottleneck for any high density and high speed VLSI circuits. In this paper we have proposed...
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