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Charge-pump phase-locked loop (CP-PLL) is one of RF circuits, which is widely used to generate timing or reference signals in communication systems, needs to be verified correctly. This paper proposes a low-cost design-for-testability (DFT) structure for a classical CP-PLL circuit to allow simple digital testing. The proposed DFT structure uses the existing circuit units as one part of test device...
Mixed-signal testing is becoming an important issue that affects both the time-to-market and product cost of many SoCs. This paper presents an effective Built-in Self-Test (BIST) method of Charge-Pump Phase-Locked Loops (CP-PLL) which is a mixed-signal circuit widely used in most of SoCs. This BIST will use the existing circuits units as test device in the test mode. It can be easily implemented with...
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