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Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of network on chip, which are called rr-path, rr-dist and rr-al respectively, rr-path schedules the NoC traffic according to the distance between the source node and the destination node, and...
Network-on-chip (NoC) is a promising solution for efficient interconnection between processor cores in chip-multi-processor (CMP). This paper is focusing on the energy-efficient design of buffers, a group of the most important components in NoC. From our investigation, an overwhelming majority of "zero" is contained in the packets transmitting in NoC for CMP. A zero-efficient buffer design...
Network-on-chip (NoC) has been proved to be an efficient solution for interconnection between processor cores in chip multi-processor (CMP), which will consume extra energy. This paper is focusing on the energy-efficient design of input buffer, one of the most critical components in NoC. For precise calculation of energy, data-transition oriented model with multilevel simulations is proposed here...
In recent years, the power efficiency of NoC (network on chip) is becoming a new research direction. For tiled CMP (single-chip multi processor), the characteristics of transmission data of NoC in a tiled CMP should be noticed that the probability of which the transmitted bits are zero is much bigger than that of which the bits are one. This paper proposes an innovative power-efficient architecture...
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