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A frequency synthesizer combining offset phase-locked loop (OPLL) and direct-digital synthesis (DDS) is presented in this paper. DDS is for channel selection as it inherits fast settling and fine resolution characteristics. OPLL structure helps to lower the DDS operation speed thus reduce the power dissipation. Compared with the conventional PLL, this structure relieves the tradeoff between loop bandwidth...
This work presents bidirectional transceiver for on-chip long wires. The current signals are transmitted bidirectional on the interconnection to double the data rate. The voltage swing on the wire is reduced so that the proposed scheme consumes less power at higher data rate. Using 0.18-mum device models for simulation, the proposed scheme has 1.25-6.80 times of date rate and 37-52% reduction of power/data...
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