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Application performance on these processor array platforms is highly sensitive to how functionality is physically placed on the device, as this choice crucially determines communication latencies and congestion patterns of the on-chip inter-core communication. The problem of identifying the best, or just a good enough, partitioning and placement does not, in general, admit to an analytic solution,...
This paper presents a new approach to buffer dimensioning for dynamic dataflow implementations. A novel transformation applied to the execution trace graph of a dataflow program is introduced in order to generate an event driven system. It is shown how model predictive control theory techniques can be applied to such a system to analyse the execution space of a dataflow program and to define and to...
The increasing ubiquity of heterogeneous parallel computing platforms nowadays creates the challenge to fully exploit the available computational power when porting existing programs or developing new applications with portability in mind. Existing design space exploration methods focus on specialized applications amenable to compile-time analysis. Real-world applications, however, tend to exhibit...
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