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A novel design scheme using neuron-MOS dynamic literal circuit and double pass-transistor logic(DPL), to realize voltage-mode dynamic ternary logic gate, is proposed. The double pass-transistor used to transmit ternary signal is controlled by the output of the dynamic literal circuit to realize ternary logic function. The complementarity and duality principles for generation of dynamic ternary complementary...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The...
A novel Schmitt trigger with controllable hysteresis using neuron-MOS transistors is presented. By selecting the ratio of capacitive coupling coefficients, a Schmitt trigger with different hysteresis characteristics can be achieved. By only varying the external input control signals, the hysteresis window can be conveniently moved without changing its width. The proposed Schmitt trigger has considerable...
The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32-nm bulk CMOS technology was studied using I- V characteristics and charge pumping measurements. The impact of stress on drain saturation current (Idsat), threshold voltage (Vt), transconductance peak (gm), and subthreshold swing (SS) is reported. For ESD stress applied on the drain, little...
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