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A ΔΣ DLL targeted for clock synchronization has been proposed. Unlike other existing ΔΣ DLL designs, the proposed DLL makes use of the ΔΣ dithering in the feedback path rather than at the input, which eliminates the need of additional multi-phase generator, and hence simplifies the architecture and improves the jitter performance. It also employs a second order adaptive filter to achieve dynamic loop...
This paper presents a new method to use correlator in modern communications after analysing the application and performance of the traditional correlator in detail. According to the results of simulation, the new method have more precise frequency and timing synchronization in wireless communications, which improves its ability against interference of multipath and frequency selective fading. Even...
In this paper, a fully frequency-domain digital ultra-wideband receiver is proposed based on the Analog-to-Digital conversion in the frequency domain. This frequency-domain receiver architecture can dramatically reduce the A/D converter (ADC) speed requirements compared with conventional time-domain ADC. Frame synchronization, channel estimation and demodulation algorithms in the frequency domain...
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