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This paper presents a novel register file with self-indexed features, targeting the DSP/media algorithm with massive data locality. The self-indexed register file (SIRF) contains 128 high-speed registers, 4 input ports and 4 output ports. It can be accessed with the double circular window mode, or simply with the immediate index mode. SIRF can eliminate write after write (WAW) dependence without register...
This paper presents a reconfigurable application specific integrated circuit (ASIC) like image interpolation implementation method. Parallel data flow and pipeline structure are used and optimized for efficient hardware acceleration. The coefficients could be easily reconfigured to support multiple interpolation filter taps and image resolution. We implement this method on a reconfigurable mathematical...
As the feature size of the semiconductor process is scaling down to 10nm and below, it is possible to assemble systems with high performance processors that can theoretically provide computational power of up to tens of PLOPS. However, the power consumption of these systems is also rocketing up to tens of millions watts, and the actual performance is only around 60% of the theoretical performance...
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