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Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have...
A new differential Voltage-Controlled Delay Unit (VCDU) is proposed. The VCDU converts an input voltage into a pulse delay, and delivers it to a Time-to-Digital Converter (TDC) which outputs a digital word. Both circuits form a Time-Based Analog-to-Digital Converter (ADC). In scaled CMOS technology, the Time-Based ADC is a substantial block in designing Software Defined Radio (SDR) receivers, as it...
This paper presents the generalization of a delayed version of the logistic map. The effect of the added two general parameters is studied, which offers the option of having three different maps. The dynamic behavior of the vertical, zooming and the general map is analyzed. The study of the fixed points, stability ranges and bifurcation diagram of the delayed logistic map at hand is detailed in this...
Time-Based Analog-to-Digital Converter (ADC), at scaled CMOS technology, plays a major role in designing Software Defined Radio (SDR) receivers as it manifests higher speed and lower power than conventional ADCs. Time-Based ADC includes a Voltage-to-Time converter (VTC) which converts the input voltage into a pulse delay, and a Time-to-Digital Converter which converts the pulse delay into a digital...
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