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Test failure data produced during post-silicon validation contain accurate design- and process-specific information about the DUD (design-under-debug). Prior research efforts and industry practice focused on feeding this information back to the design flow via bug root-cause analysis. However, the value of this silicon data for helping further improvement of the post-silicon validation process has...
There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently...
Electrical bugs, such as those caused by crosstalk or power droop, are a growing concern due to shrinking noise margins and increasing variability. This paper introduces COBE, an electrical bug modeling technique which can be used to evaluate the effectiveness of validation tests and DfD (design-for-debug) structures for detecting these errors in post-silicon validation. COBE first uses gate-level...
Post-silicon debugging has become the least predictable and most labor-intensive step in the modern design flow at 65nm and below. In this paper, we present a design-for-debug (DfD) technique - named Time-Multiplexed Assertion Checking (TMAC) - for post-silicon bug detection and isolation. By instantiating assertion checkers in an on-chip reconfigurable block (either an embedded FPGA block or a spare...
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