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This paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering...
This paper presents practical implementations of test cores for analog and mixed-signal BIST. A sinewave generator for test stimulus generation, and a periodical signal characterization system for response evaluation are discussed. Integrated prototypes and experimental results are provided, and a prototype of a network/spectrum analyzer featuring both test cores has been developed and tested in the...
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