The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A GaAs low power Buffered FET Logic (BFL) 4-bit ripple carry adder is presented. Preliminary performance measurements indicate a critical path average propagation delay of 1.9 ns at a total power dissipation of 45 mW, output buffers included. This corresponds to an average propagation delay of 380 ps/gate (FI/ FO = 5/3), an average power consumption of 1.5 mW/gate, and a power-delay product of 0.6...
Master-slave binary frequency dividers have been designed and implemented with enhancement-mode GaAs MESFETs by using the so-called LPFL logic approach. A wide range of speed-power performances has been observed: a maximum toggle frequency of 2.8 GHz at P = 15 mW/gate on a dual-clocked frequency divider and an fc,max of 1.73 GHz at Pxtpd = 1 pJ/gate on a single-clocked one. The high-speed performance...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.