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The performance of organic thin film transistors (OTFTs) with dual pentacene channel layer (DL) has been studied. Silvaco ATLAS is used to simulate the influence of different device structure parameters. The result shows that the variation in contact placement, thickness of high mobility pentacene layer, the total thickness of two pentacene layers and the height of source and drain result in different...
Noninvasive visualization of blood flow with high frequency Doppler ultrasound has been extensively used to assess the morphology and hemodynamics of the microcirculation. A completely digital implementation of multi-gate pulsed-wave (PW) Doppler method was proposed in this paper for high frequency ultrasound applications. Analog mixer was eliminated by a digital demodulator and same data acquisition...
The DC and analog/RF performance of p-channel Schottky barrier Si and Ge nanowire transistors are simulated and some impact factors are studied. The results suggest that 100meV and 50meV are the most optimized Schottky barrier height for intrinsic gain and cutoff frequency respectively. Thinner nanowires enhance the drivability of silicon devices while impair that of germanium devices. With gate length...
The performance of n-channel gate-all-around silicon nanowire FETs with asymmetric barrier heights at source/drain (ASB-SiNW-FET) was simulated. Some impact factors are studied. The results suggest that the drain current and threshold voltage are mainly determined by source-side barrier height (S-SBH). Increasing S-SBH or decreasing nanowire radius can optimize sub-threshold slope, while decreasing...
The mismatch of trapped electrons and holes is the main mechanism causing reliability degradation for localized charge trapping memory devices. This paper proposes a novel dual-BBHH erasing scheme to alleviate the mismatch effect, therefore improve the endurance and retention performances simultaneously.
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