The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Electric vehicles and hybrid electric vehicles are rapidly gaining popularity as an important means of decarbonizing the transport sector in tackling sustainable energy supply and environment pollution problems. To build a proper battery model is essential in predicting battery behaviour under various operating conditions for avoiding unsafe battery operations and in developing proper controlling...
In this paper a multithreaded processor with hardware context switch mechanism driven by external events is presented for multi-processor system on chip (MPSoC). Combining this mechanism with asynchronous memory access the proposed processor implements Non-preemptive thread scheduling which can assure fairness of threads and optimization for single thread. The overhead of hardware thread switch is...
This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A `ping-pong' structure is adopted in SRAM interface logic which optimizes the memory data throughput...
In this paper an bus architecture combining crossbar switching with split transaction feature is presented for multiprocessor system on chip (MPSoC) in the packet processing application. The high throughput is achieved with crossbar bus topology and low bus latency is finished by split transaction buses which separate address bus from data one. Experimental results show that performance of the proposed...
An integrated SDRAM controller with asynchronous access architecture is proposed. The controller takes charge of data transfer between off-chip SDRAM memory and the multicore multithreaded processors. The interleaving optimization for opposite bank is incorporated into the SDRAM controller, which can reduce memory latency and improve the memory bus performance. FPGA results show that the proposed...
In a memory structure shared by multiple processors based on Multiprocessor Systems on Chip (MPSoC), the efficiency of memory bus access becomes the bottleneck of the overall system efficiency. This paper presents a low-latency SDARM controller structure integrated in MPSoC, which controls the off-chip SDRAM memory. Consecutive same row optimization and odd-even bank optimization are used to eliminate...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.