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This paper present a parallel, split bus interconnection scheme for the multi-processor system. The scheme provides a command bus and a set of data bus, each of which works independently. This bus interconnect scheme can greatly improve the bandwidth of data communication within the multi-processor system because of its characteristics of concurrency and separability.
In this paper, we propose a cost-effective way to improve the performance of DRAM based on multi-core system. A novel DRAM controller with instruction prefecthing mechanism is introduced. The controller dynamically selects Open Page(OP) or Close Page(CP) policy by getting some information of future accesses in advance. This DRAM controller with dynamic policy based on instruction prefetching(DP_BIF),...
High performance routers require fast packet buffers to hold packets awaiting transmission[1]. These buffers usually use a memory hierarchy that consist of expensive but fast SRAM and cheap but slow DRAM to meet both, speed and capacity requirements[2]. In this paper, we introduce a particular memory hierarchy as packet buffer architecture which consists of multiple, independent memory channels of...
The study in this paper is aimed at improving the performance of a network processor design (XDNP) based on a Virtex-4 FPGA by using the PlanAhead tool offered by XILINX. PlanAhead gives a unique visibility into the design. The tool can very quickly identify the critical path, and then supply hierarchical floorplanning to achieve faster timing closure. XDNP is targeted at networking applications requiring...
This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A `ping-pong' structure is adopted in SRAM interface logic which optimizes the memory data throughput...
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