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This paper demonstrates a 17.5-Gb/s complete transceiver with a MaxEye-based autonomous adaptation of equalization in a 40-nm CMOS process. The output stage of the transmitter employs 3-tap finite-impulse response (FIR) equalization. The receiver compensates the attenuation of the cable with a 2-stage continuous time linear equalizer (CTLE) and 5-tap decision-feedback equalizer (DFE). Based on the...
We proposed an on-chip jitter injection circuit embedded in phase-locked-loop for jitter tolerance test of clock and data recovery circuit. The proposed jitter modulation block consists of divider, signal modulator, and modulating charge pump to inject the sinusoidal voltage to the VCO control voltage. Jitter modulation frequency and amplitude cover the jitter tolerance mask for DisplayPort v1.2 from...
We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The DC-coupled receiver front-end circuits deal with the common-mode level variations and compensate for the channel loss. The tracked oversampling CDR which realizes...
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