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In this paper, a 12-bit CMOS digital-to-analog converter (DAC) which provide a stable bias voltage to eliminate the influence of gravitat ional acceleration is presented. The dual-ladder resistor-string structure is adopted for the DAC core. In addition, a low-noise class-AB output buffer is proposed in which the circuit uses chopper stabilization (CHS) technique for the suppression of the low-frequency...
A robust ESD device for 5V circuit protection was designed and fabricated in a 0.5-µm 5V CDMOS process. It is composed of multi-fingered GCNMOS and ballasting-resistor. The ESD performance of such device with strip layout style is investigated by employing transmission line pulse (TLP) measurement. A double-triggered phenomenon is detected in the multi-fingered GCNMOS with ballasting-resistor. And...
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