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We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=1.0V). Pulsed I-V measurements provide small SS and record I60 of 1×10−2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION. Transient analysis of complementary TFET inverters demonstrates...
Tunneling field-effect transistors (TFETs) were fabricated from compressively strained Si/SiGe wafers with a stepped gate to enhance band to band tunneling. In-situ highly p-doped Si0.5Ge0.5 was used as source and As-implanted Si as drain. For the gate stack, conformal HfO2 (k = 22) and TiN were deposited, which resulted in an effective oxide thickness (EOT) of ∼ 1nm. The TFET devices exhibit minimum...
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