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This paper presents two novel architectures for two-dimensional (2-D) Haar wavelet transform (HWT) of transform block in face recognition systems. The proposed architectures comprises 2-D HWT with transpose-based computation and dynamic partial reconfiguration (DPR) that have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. To evaluate the proposed architecture, comparison for...
This paper describes a new dynamic partial reconfiguration (DPR) design flow and environment for image processing algorithms. The functionality and design techniques are demonstrated through an efficient implementation of colour space conversion (CSC) intellectual property (IP) core used in many image processing applications such as compression. Furthermore, an evaluation and application flow example...
The development of the security layers between the wireless terminals is one of the biggest trends in wireless communications. Bluetooth can be described as the short range and the low power supplements that holds the connection protocol through various devices. This paper presents the development of a secure wireless connection terminals on a field programmable gate array (FPGA). The wireless connection...
This paper describes the design and implementation of 3D Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR). As a result of the separability property of the multi-dimensional HWT, the proposed architecture has been implemented using a cascade of three N-point 1D HWT and two transpose memory for a 3D volume of N ?? N ?? N, suitable for 3D medical...
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