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High performance computing (HPC) systems currently integrate several resources such as multi-cores (CPUs), graphic processing units (GPUs) and reconfigurable logic devices, like field programmable gate arrays (FPGAs). The role of the latter two has traditionally being confined to act as secondary accelerators rather than as main execution units. We perform a deep survey around state of the art research...
Branch-and-Bound (B&B) algorithms are one of the most employed techniques in optimization problems. Its complexity increases exponentially with problem size and features a challenging dynamic memory management caused by recursive processing. Most solutions focus on parallel branch evaluation in multi-core CPUs or GPUs. To the best of our knowledge, to the date, no works have employed FPGAs to...
FPGA-based platforms allow implementing reconfigurable systems that can change functionality of portions of hardware at runtime. For this purpose, non-volatile, off-chip storage is required to hold the partial-configuration bitstreams that will be used for reconfiguration. Accessing such devices requires a high CPU usage or a dedicated hardware such as a Direct Memory Access (DMA) module, especially...
With the rapid development of the new generation of DNA sequencers, the rate of data generation is rapidly outpacing the rate at which it can be computationally processed. Traditional sequence alignment based on PC cannot meet this growing demand. Accelerate the algorithm execution using reconfigurable architectures such as FPGAs provides better performance compared to other platforms. This paper...
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