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Constructed from a current reused architecture for low power consumption, a cascode topology of an LC VCO and a divide-by-4 prescaler is used in a PLL. In the prescaler, the first-stage divide-by-2 divider is an injection locking circuit used to frequency lock to an incident signal to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing...
To lower the supply voltage for high-frequency operation, a fully integrated frequency synthesizer, together with regenerative frequency-doubling and fractional phase-rotating techniques, is presented. The frequency-doubling circuit regenerates the tail signals at twice the frequency of the quadrature voltage-controlled oscillator (QVCO) to achieve larger output swing and higher operating frequency...
The paper presents a low-voltage design for a high frequency phase-locked loop (PLL) implemented in standard 0.13-µm CMOS technology. The PLL has fractional function through a high-speed phase-rotating operation. In order to provide more high-frequency output, a frequency doubler is employed at the output stage of the voltage-controlled oscillator (VCO). Through the introduction of the transformers,...
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