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This paper identifies and addresses key design considerations and trade-offs in the implementation of a CMOS high-resolution microheater array for Lab-on-Chip (LOC) applications. Specifically, this is investigated in the context of facilitating the in vitro thermal stimulation of single neurons. The paper analyses the electro-thermal response (by means of COMSOL simulations) and reliability issues...
A design of low-power voltage detector (VD) based on current comparison technology is presented. This VD samples the power supply voltage and converts the sampled voltage to a current which will be compared with a reference. The current comparison technology simplifies the design without use of the resistor string and voltage comparators, and thus reduces the core area. The VD detects three thresholds...
Multi-bit delta-sigma (????) modulators suffer from the nonlinearity of feedback digital-analogue converters (DACs) caused by component mismatch. Traditional dynamic element matching techniques are limited in speed owing to the feedback delay. The proposed interleaved data weighted averaging (I-DWA) technique relaxes this speed requirement and therefore allows either a higher bandwidth or improved...
A 9 GHz fully digitally controlled oscillator implemented in 65 nm CMOS technology is presented. This is the first DCO implemented at 9 GHz which covers all transmitter (TX) and receiver (RX) bands of GSM/EDGE and UMTS except Band VII. It covers a coarse tuning range from 6.35 GHz to 9.15 GHz which is realized by binary weighted switchable capacitors. The phase noise performance meets the specifications...
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