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To reach future low power operation at ⩽0.5 V, high mobility InGaAs nMOS and Ge pMOS were proposed at sub-14 nm nodes. However, the integration of InGaAs on Si faces difficult challenges of the large 8% lattice-mismatch, high dislocation densities, and antiphase domain boundaries. Although the defect-free Ge-on-Insulator (GOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI) on Si, and selective...
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