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Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related...
Speedpath debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speedpath debug based on functional patterns can be very expensive. In this paper, we explore scan-based speedpath debug techniques based on at-speed scan test patterns. Several enhancements are implemented to improve over an earlier proposed scan-based speedpath diagnosis algorithm...
The use of low-cost structural Fmax measurement as a replacement for in-system Fmax measurement for speed binning has been aided by the use of a data-learning approach that can be used to build a reliable single-core system Fmax predictor given structural Fmax. This paper uses industry test measurements to demonstrate how the data-learning approach can be applied to predict multi-core system Fmax,...
The detection of speed-related defects relies on fault excitation and propagation along critical speed paths in the design. Different types of structural tests detect speed paths differently. In this paper, we compare the capabilities of speed path detection using Ndetect and timing-aware transition tests on silicon. Experimental data on the latest quad-core AMD Opteron?? processor is collected. Results...
System test has been the standard measurement to evaluate performance variability of high-performance microprocessors. The question of whether or not many of the lower-cost alternative tests can be used to reduce system test has been studied for many years. This paper utilizes a data-learning approach for correlating three test datasets, structural test, ring oscillator test, and scan flush test,...
Speed path identification is an indispensable step for pushing the design timing wall. We propose a new at-speed diagnosis methodology. Key characteristics of the methodology are (a) path-oriented diagnosis, (b) failing frequency guided, and (d) identified speed paths referenced in the timing verification design database. We demonstrate the effectiveness of our technique on a quad-core AMD Opteron??...
The question of whether or not structural test measurements can be used to predict functional or system Fmax, has been studied for many years. This paper presents a data learning approach to study the question. Given Fmax values and structural delay measurements on a set of sample chips, we propose a method called conformity check whose goal is to select a subset of conformal samples such that a more...
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